MC68030 Datasheet, PDF (447/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Instruction Execution Timing
The instructions that require the instruction-cache case, head, and tail of an effective
address (CCea, Hea, and Tea) to be overlapped with CCop, Hop, and Top are footnoted in
11.6 Instruction Timing Tables.
The actual instruction-cache-case execution time for a stream of instructions can be
computed using Equation (11-1) or the general Equation (11-2). Equation (11-1) is used
unless the instruction-cache case, head, and tail of an effective address are required.
An example using a series of instructions that require Equation (11-1) to calculate the
instruction-cache-case execution time follows. The assumptions referred to in 11.6
Instruction Timing Tables apply.
Instruction
1. ADD.L
2. SUBA.L
A1,D1
D1,A2
Referring to the timing table in 11.6.8 Arithmetical/Logical Instructions, the head, tail, and
instruction-cache-case (CC) times for ADD.L A1,D1 and SUBA.L D1,A2 are found. There is
no footnote directing the user to add an effective address time for either instruction. Since
both of the instructions use register operands only, there is no need to add effective address
calculation times. Therefore, the general Equation (11-1) can be used for both.
Head
Tail
CC
1.ADD.L A1,D1
2.SUBA.L D1,A2
2
0
2
4
0
4
NOTE
The underlined numbers show the typical pattern for the com-
parison of head and tail in the following equation.
The following computations use Equation (11-1):
Execution Time
= CC1+[CC2-min(H2,T1)]
= 2+[4-min(4,0)]
= 2+[4-0]
= 6 clocks
11-12
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