MC68030 Datasheet, PDF (506/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Applications Information
• DSACK1, DSACK0 = Data transfer and size acknowledge. Driven by an asynchronous
port to indicate the actual bus width of the port.
• STERM = Synchronous termination. Driven by a 32-bit synchronous port only.
The MC68030 assumes that 16-bit ports are situated on data lines D16–D31, and that 8-bit
ports are situated on data lines D24–D31. This ensures that the following logic works
correctly with the MC68030's on-chip internal-to-external data bus multiplexer. Refer to
Section 7 Bus Operation for more details on the dynamic bus sizing mechanism.
The need for byte select signals is best illustrated by an example. Consider a long-word
write cycle to an odd address in word-organized memory. The transfer requires three bus
cycles to complete. The first bus cycle transfers the most significant byte of the long word
on D16–D23. The second bus cycle transfers a word on D16–D31, and the last bus cycle
transfers the least significant byte of the original long word on D24–D31. In order not to
overwrite those bytes which are not used these transfers, a unique byte data strobe must be
generated for each byte when using devices with 16- and 32-bit port widths.
For noncachable read cycles and all write cycles, the required active bytes of the data bus
for any given bus transfer are a function of the size (SIZ0/SIZ1) and lower address (A0/A1)
outputs and are shown in Table 12-1. Individual strobes or select signals can be generated
by decoding these four signals for every bus cycle. Devices residing on 8-bit ports can utilize
data strobe (DS) alone since there is only one valid byte for any transfer.
During cachable read cycles, the addressed device must provide valid data over its full bus
width (as indicated by DSACKx or STERM). While instructions are always prefetched as
long-word-aligned accesses, data fetches can occur with any alignment and size. Because
the MC68030 assumes that the entire data bus port size contains valid data, cachable data
read bus cycles must provide as much data as signaled by the port size during a bus cycle.
To satisfy this requirement, the R/W signal must be included in the byte select logic for the
MC68030.
Figure 12-6 shows a block diagram of an MC68030 system with two memory banks. The
PAL provides memory-mapped byte select signals for an asynchronous 32-bit port and
unmapped byte select signals for other memory banks or ports. Figure 12-7 provides sample
equations for the PAL.
MOTOROLA
MC68030 USER’S MANUAL
12-9