MC68030 Datasheet, PDF (481/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Instruction Execution Timing
11.6.13 Bit Manipulation Instructions
The bit manipulation instruction table indicates the number of clock periods needed for the
processor to perform the specified bit operation on the given addressing mode. Footnotes
indicate when it is necessary to account for the appropriate effective address time. For
instruction-cache case and for no-cache case, the total number of clock cycles is outside the
parentheses. The number of read, prefetch, and write cycles is given inside the parentheses
as (r/p/w). The read, prefetch, and write cycles are included in the total clock cycle number.
All timing data assumes two-clock reads and writes.
Instruction
BTST
#〈data〉,Dn
BTST
Dn,Dn
#
BTST
#〈data〉,Mem
*
BTST
Dn,Mem
BCHG
#〈data〉,Dn
BCHG
Dn,Dn
#
BCHG
#〈data〉,Mem
*
BCHG
Dn,Mem
BCLR
#〈data〉,Dn
BCLR
Dn,Dn
#
BCLR
#〈data〉,Mem
*
BCLR
Dn,Mem
BSET
#〈data〉,Dn
BSET
Dn,Dn
#
BSET
#〈data〉,Mem
*
BSET
Dn,Mem
Head
Tail
4
0
4
0
0
0
0
0
6
0
6
0
0
0
0
0
6
0
6
0
0
0
0
0
6
0
6
0
0
0
0
0
* Add Fetch Effective Address Time
# Add Fetch Immediate Effective Address Time
I-Cache Case
4(0/0/0)
4(0/0/0)
4(0/0/0)
4(0/0/0)
6(0/0/0)
6(0/0/0)
6(0/0/1)
6(0/0/1)
6(0/0/0)
6(0/0/0)
6(0/0/1)
6(0/0/1)
6(0/0/0)
6(0/0/0)
6(0/0/1)
6(0/0/1)
No-Cache Case
4(0/1/0)
4(0/1/0)
4(0/1/0)
4(0/1/0)
6(0/1/0)
6(0/1/0)
6(0/1/1)
6(0/1/1)
6(0/1/0)
6(0/1/0)
6(0/1/1)
6(0/1/1)
6(0/1/0)
6(0/1/0)
6(0/1/1)
6(0/1/1)
11-46
MC68030 USER’S MANUAL
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