MC68030 Datasheet, PDF (346/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Memory Management Unit
9.9.3 Impact of MMU Features On Table Definition
The features of the MMU that impact table definition are usually considered after deciding
how to map memory for the tasks. For some systems, these features can affect the mapping
decision and should be considered when making that decision.
9.9.3.1 NUMBER OF TABLE LEVELS. The MMU supports from zero to five levels (six
levels with the use of indirection) in the address translation tables. The zero-level case is
early termination at the root pointer. This provides a limit check on the range of physical
addresses for the system. It is used primarily in systems that require the limit check on
physical addresses.
Systems that support large page sizes or that require only limited amounts of virtual memory
space can use single-level tables. A single-level translation tree with 32K-byte pages may
be the best choice for systems that are primarily numerically intensive (i.e., the system is
involved in arithmetic manipulations rather than data movement) where the overhead of
virtual page faults and paging I/O must be minimized. This type of system can map a 16-
Mbyte address space with only 2K bytes of page table space. With this much mapped
address space, table search time becomes insignificant.
At another extreme is a single-user business system that only needs a 2-Mbyte[lz virtual
address space. A 512-byte page size might be best for this system, because the block size
formats of many Winchester hard disk file systems is 512 bytes. A page table that
completely maps the 2-Mbyte space requires only 16K bytes of memory, and the ATC
entries directly map 11K bytes of virtual space at any one time. The page tables for this
system and the one described in the preceding paragraph are small enough to be
permanently allocated in the operating system data area. They incur virtually no
management or swapping overhead.
A two-level address translation table provides a lower page level similar to the page tables
in the two preceding paragraphs and additional direction at a higher level. For example, in
a system using 32K-byte pages and 512-entry page tables, the upper level translation table
contains 256 entries of short-format descriptors, requiring 1K bytes for the table. Each of the
upper table entries maps a 16-Mbyte region of the virtual address space. The primary
advantage of a two-level table for large "number-crunching" system is the operating system
designer's ability to make a tradeoff between page size and table size. The system designer
may choose a smaller page size to fit the block sizes on available I/O devices, yet keep the
tables manageable. However, the designer must also consider the performance penalty
associated with smaller page sizes. Systems with smaller page sizes have a higher
frequency of page faults requiring more table search time and paging I/O. With the flexibility
of the MC68030 MMU, the designer has enough choices to optimize table structure design
and page size.
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MC68030 USER’S MANUAL
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