MC68030 Datasheet, PDF (201/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Bus Operation
CLK
A31-A0
S0 S1 S2 Sw Sw S3
FC2-FC0
SIZ1
SIZ0
R/W
ECS
OCS
AS
DS
DSACK1
DSACK0
STERM
CIIN
CIOUT
CBREQ
CBACK
D31-D0
DBEN
Figure 7-34. Synchronous Write Cycle with Wait States — CIOUT Asserted
State 2
During S2, the processor places the data to be written onto D0–D31. The selected device
uses R/W, CLK, SIZ0–SIZ1, and A0–A1 to latch data from the appropriate section(s) of
the data bus (D24–D31, D16–D23, D8–D15, and D0–D7). SIZ0–SIZ1 and A0–A1 select
the data bus sections. The device asserts STERM when it has successfully stored the
data. If the device does not assert STERM by the rising edge of S2, the processor inserts
wait states until it is recognized. The processor asserts DS at the end of S2 if wait states
are inserted. For zero-wait-state synchronous write cycles, DS is not asserted.
MOTOROLA
MC68030 USER’S MANUAL
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