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| MC68030 Datasheet, PDF (492/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR | |||
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xSLxx
xLSxx
xLLxx
xSSSx
xSSLx
xSLSx
xSLLx
xLSSx
xLSLx
xLLSx
xLLLx
40/3/2
42/3/2
43/4/2
48/3/3
49/4/3
51/4/3
52/5/3
51/4/3
52/5/3
54/5/3
55/6/3
36/3/1
38/3/1
39/4/1
40/3/1
41/4/1
43/4/1
44/5/1
43/4/1
44/5/1
46/5/1
47/6/1
Instruction Execution Timing
34/3/0
36/3/0
37/4/0
38/3/0
39/4/0
41/4/0
44/5/0
41/4/0
42/5/0
44/5/0
45/6/0
11.7.1 MMU Effective Address Calculation
The calculate effective address table for MMU instructions lists the number of clock periods
needed for the processor to calculate various effective addresses. Fetch time is only
included for the first level of indirection on memory indirect addressing modes. The total
number of clock cycles is outside the parentheses. This total includes the number of read,
prefetch, and write cycles, which are shown inside the parentheses as (r/pr/w).
(An)
(d16,An)
(xxx).W
(xxx).L
(d8,An,Xn)
Address Mode
FULL FORMAT EXTENSION WORD(S)
(d16,An)
(d16,An,Xn)
([d16,An])
([d16,An],Xn)
([d16,An],d16)
([d16,An],Xn,d16)
([d16,An],d32)
([d16,An],Xn,d32)
(B)
(d16,B)
(d32,B)
([B])
([B],I)
([B],d16)
([B],I,d16)
([B],d32)
([B],I,d32)
([d16,B])
([d16,B],I)
Head
4+op head
4+op head
4+op head
6+op head
4+op head
4
4
4
4
2
4
4
4
8+op head
6
6
6
6
6
6
6
6
6
6
Tail
I-Cache Case
No-Cache
Case
0
4(0/0/0)
4(0/1/0)
0
4(0/0/0)
4(0/1/0)
0
4(0/0/0)
4(0/1/0)
0
6(0/0/0)
6(0/2/0)
0
4(0/0/0)
4(0/1/0)
0
8(0/0/0)
8(0/2/0)
0
8(0/0/0)
8(0/2/0)
0
12(1/0/0)
12(1/2/0)
0
12(1/0/0)
12(1/2/0)
0
12(1/0/0)
12(1/2/0)
0
12(1/0/0)
12(1/2/0)
0
14(1/0/0)
14(1/3/0)
0
14(1/0/0)
14(1/3/0)
0
8(0/0/0)
8(0/1/0)
0
10(0/0/0)
10(0/2/0)
0
16(0/0/0)
16(0/2/0)
0
12(1/0/0)
12(1/1/0)
0
12(1/0/0)
12(1/1/0)
0
12(1/0/0)
12(1/2/0)
0
12(1/0/0)
12(1/2/0)
0
14(1/0/0)
14(1/2/0)
0
14(1/0/0)
14(1/2/0)
0
14(1/0/0)
14(1/2/0)
0
14(1/0/0)
14(1/2/0)
MOTOROLA
MC68030 USERâS MANUAL
11-57
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