MC68030 Datasheet, PDF (451/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Instruction Execution Timing
Use the general Equation (11-2) to compute:
Execution Time:
= CCea1+[CCop1-min(Hop1,Tea1)]+[CCea2-min(Hea2,Top1)]+
[CCop2-min(Hop2,Tea2)]+[CCea3-min(Hea3,Top2)]+
[CCop3- min(Hop3,Tea3)]
= 2+[44-min(2,0)]+[6-min(4,0)]+[14-min(6,2)]+[6 -min(6,0)]+
[90 -min(0,0)]
= 2+44+6+12+6+90
= 60 clock periods
NOTE
This CC time is a maximum since the times given for the MU-
LU.L and DIVS.L are maximums.
11.4 EFFECT OF DATA CACHE
When the data accesses required by an instruction are in the data cache, reading these
operands requires no bus cycles, and the execution time for the instruction may be
minimized. Write accesses, however, always require bus cycles because the data cache is
a write through cache.
The effect of the data cache on operand read accesses can be factored into the actual
instruction execution time as follows.
When a data cache hit occurs for the data fetch corresponding to either the fetch effective
address table or the fetch immediate effective address table in 11.6 Instruction Timing
Tables, the following rules apply:
1a. if Tail_t = 0:
1b. f Tail_t = 1:
1c. f Tail_t>1:
where:
No change in timing.
Tail = Tail_t–1
CC = CC_t–1
Tail = Tail_t–(Tail_t–1) = 1
CC = CC_t–(Tail_t–1)
Tail_t and CC_t are the values listed in the tables.
2. If the EA mode is memory indirect (two data reads), the tail and CC time are calculated
as for one data read.
11-16
MC68030 USER’S MANUAL
MOTOROLA