MC68030 Datasheet, PDF (529/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Applications Information
(UNABLE TO LOCATE ART)
Figure 12-18. Example Early Termination Control Circuit
The late termination circuit is formed by the gates (D) and (E). If the current cycle is
accessing a cachable location, as determined by the output of (C), and a cache hit has not
occurred (D), then the BERR and HALT signals are driven low (E).
Note that the logic depicted in Figure 12-18 is designed to support a cache operating with
no wait states. A provision for generating wait states may be included by placing additional
timing stages between (C) and the MC68030 to delay propagation of this output by the
required number of clock periods.
MOTOROLA
MC68030 USER’S MANUAL
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