MC68030 Datasheet, PDF (292/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Memory Management Unit
31
0
ACCESS CONTROL 0
31
0
ACCESS CONTROL 1
15
0
ACU STATUS (ACUSR)
FIG. 9-2
Figure 9-2. MMU Programming Model
The ATC in the MMU is a fully associative cache that stores 22 logical-to-physical address
translations and associated page information. It compares the logical address and function
code internally supplied by the processor with all tag entries in the ATC. When the access
address and function code matches a tag in the ATC (a hit occurs) and no access violation
is detected, the ATC outputs the corresponding physical address to the bus controller, which
continues the external bus cycle. Function codes are routed to the bus controller unmodified.
Each ATC entry contains a logical address, a physical address, and status bits. Among the
status bits are the write protect and cache inhibit bits.
When the ATC does not contain the translation for a logical address (a miss occurs) and an
external bus cycle is required, the MMU aborts the access and causes the processor to
initiate bus cycles that search the translation tables in memory for the correct translation. If
the table search completes without any errors, the MMU stores the translation in the ATC
and provides the physical address for the access, allowing the bus controller to retry the
original bus cycle.
An MMU translation table has a tree structure with the base of the first table defined by a
root pointer descriptor. The root pointer descriptor of the current translation table is resident
in one of two root pointer registers. The general tree structure is shown in Figure 9-3. Table
entries at the upper levels of a tree point to other tables. The table leaf entries are page
frame addresses. All addresses stored in the translation tables are physical addresses; the
translation tables reside in the physical address space.
System software selects the parameters for the translation tables by configuring the
translation control register (TC) appropriately. The function codes or a portion of the logical
address can be defined as the index into the first level of lookup in the table. The TC register
specifies how many bits of the logical address are used as the index for each level of the
lookup (as many as 15 bits can be used at a given level).
9-4
MC68030 USER’S MANUAL
MOTOROLA