MC68030 Datasheet, PDF (267/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Exception Processing
Table 8-3. Tracing Control
T1
T0
Tracing Function
0
0
No Tracing
0
1
Trace on Change of Flow (BRA, JMP, etc.)
1
0
Trace on Instruction Execution (Any Instruction)
1
1
Undefined, Reserved
In general terms, a trace exception is an extension to the function of any traced instruction
— that is, the execution of a traced instruction is not complete until the trace exception
processing is completed. If an instruction does not complete due to a bus error or address
error exception, trace exception processing is deferred until after the execution of the
suspended instruction is resumed and the instruction execution completes normally. If an
interrupt is pending at the completion of an instruction, the trace exception processing
occurs before the interrupt exception processing starts. If an instruction forces an exception
as part of its normal execution, the forced exception processing occurs before the trace
exception is processed. See 8.1.12 Multiple Exceptions for a more complete discussion of
exception priorities.
When the processor is in the trace mode and attempts to execute an illegal or
unimplemented instruction, that instruction does not cause a trace exception since it is not
executed. This is of particular importance to an instruction emulation routine that performs
the instruction function, adjusts the stacked program counter to skip the unimplemented
instruction, and returns. Before returning, the trace bits of the status register on the stack
should be checked. If tracing is enabled, the trace exception processing should also be
emulated for the trace exception handler to account for the emulated instruction.
The exception processing for a trace starts at the end of normal processing for the traced
instruction and before the start of the next instruction. The processor makes an internal copy
of the status register and enters the supervisor privilege level. It also clears the T0 and T1
bits of the status register, disabling further tracing. The processor supplies vector number 9
for the trace exception and saves the trace exception vector offset, program counter value,
and the copy of the status register on the supervisor stack. The saved value of the program
counter is the logical address of the next instruction to be executed. Instruction execution
resumes after the required prefetches from the address in the trace exception vector.
MOTOROLA
MC68030 USER’S MANUAL
8-13