MC68030 Datasheet, PDF (444/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Instruction Execution Timing
The effect of instruction alignment on timing is illustrated by the following example. The
assumptions referred to in 11.6 Instruction Timing Tables apply. Both the data cache and
instruction cache miss on all accesses.
1.MOVE.L
2.CMPI.W
Instruction
(d₁₆,An,Dn),Dn
#<data>.W,(d₁₆,An)
The instruction stream is positioned with even alignment in 32-bit memory as:
Address
n
n+4
n+8
n+12
MOVE
d₁₆
#(data. W)
...
EA Ext
CMPI
d₁₆
...
Figure 11-4 shows processor activity for even alignment of the given instruction stream. It
shows the activity of the external bus, the bus controller, and the sequencer.
1
CLOCK
BUS
ACTIVITY
23 456
PREFETCH READ
7 8 9 10 11 12 13 14 15 16
PREFETCH
READ
PREFETCH
BUS
CONTROLLER
IDLE
PREFETCH READ FROM PREFETCH
n+8
d16,An,Dn
n + 12
IDLE
READ FROM PREFETCH
IDLE
(d16,An)
n + 16
SEQUENCER
INSTRUCTION
EXECUTION TIME
CALCULATE AND FETCH
SOURCE EA
FOR MOVE
MOVE.L (d16,An,Dn),Dn
PERFORM
MOVE
CALCULATE AND FETCH
SOURCE EA
IDLE
FOR CMPI
CMPI.W #(data).W,(d16,An)
CLOCK
COUNT
8
8
LEGEND:
1) MOVE.L (d16,An,Dn),Dn
2) #(data).W,(d16,An)
Figure 11-4. Processor Activity – Even Alignment
PERFORM
CMPI
Figure 11-5 shows processor activity for odd alignment. The instruction stream is positioned
in 32-bit memory as:
Address
n
n+4
n+8
n+12
...
EA Ext
CMPI
d₁₆
MOVE
d₁₆
#(data.W)
...
MOTOROLA
MC68030 USER’S MANUAL
11-9