MC68030 Datasheet, PDF (483/602 Pages) Motorola, Inc – ENHANCED 32-BIT MICROPROCESSOR

Instruction Execution Timing
11.6.15 Conditional Branch Instructions
The conditional branch instruction table indicates the number of clock periods needed for
the processor to perform the specified branch on the given branch size, with complete
execution times given. No additional tables are needed to calculate total effective execution
time for these instructions. For instruction-cache case and for no-cache case, the total
number of clock cycles is outside the parenthees. The number of read, prefetch, and write
cycles is given inside the parentheses as (r/p/w). The read, prefetch, and write cycles are
included in the total clock cycle number.
All timing data assumes two-clock reads and writes.
Instruction
Head
Tail
Bcc
(Taken)
6
0
Bcc.B
(Not Taken)
4
0
Bcc.W
(Not Taken)
6
0
Bcc.L
(Not Taken)
6
0
DBcc
(cc = False, Count Not Expired)
6
0
DBcc
(cc = False, Count Expired)
10
0
DBcc
(cc = True)
6
0
I-Cache Case
6(0/0/0)
4(0/0/0)
6(0/0/0)
6(0/0/0)
6(0/0/0)
10(0/0/0)
6(0/0/0)
No-Cache
Case
8(0/2/0)
4(0/1/0)
6(0/1/0)
8(0/2/0)
8(0/2/0)
13(0/3/0)
8(0/1/0)
11-48
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