EW31244SL7QV Datasheet, PDF (99/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
Table 34. 31244 Controller Serial ATA Protocol and Bus Error Conditions (Sheet 2 of 2)
Bit
17
16
15-12
11
10
09
08
07:02
01
00
Description
DIAG_I - Reserved, not implemented.
DIAG_N - PHYRDY Change State:
When set to one this bit indicates that the PHYRDY signal changed state. State change means going
from ready-to-not ready or not ready-to-ready. This bit shall remain cleared when the PHY was not
detected as ready during the initialization process. When the PHY goes ready after initialization, this bit
shall transition to 1. This bit is cleared by writing a 1 to it. This bit is reported as an interrupt on bit 0, 8,
16, and 24 of the SATA Interrupt Pending register for SATA ports 0, 1, 2, and 3 respectively. Refer to
Table 116, “SU PCI DPA Interrupt Pending Register - SUPDIPR” on page 194.
The default value after reset is 0₂, for example the PHY will not be ready. When the PHY becomes
ready (state change from not ready to ready) as part of the initialization sequence, the value will change
to 1₂.
Reserved.
ERR_E - Internal Error:
This bit indicates that a FIFO error occurred due to a FIFO overrun or underrun condition. This bit is
cleared by writing a 1 to it. This bit is reported as an interrupt on bit 2, 10, 18, and 26 of the SATA
Interrupt Pending register for SATA ports 0, 1, 2, and 3 respectively. Refer to Table 116, “SU PCI DPA
Interrupt Pending Register - SUPDIPR” on page 194.
ERR_P - Protocol Error:
This bit when set indicates that a corrupted FIS was received. This bit may indicate that the FIS
received was an invalid FIS type or that the received FIS was not properly structured. For example,
incorrect length. This bit is cleared by writing a 1 to it. This bit is reported as an interrupt on bit 4, 12, 20,
and 28 of the SATA Interrupt Pending register for SATA ports 0, 1, 2, and 3 respectively. Refer to
Table 116, “SU PCI DPA Interrupt Pending Register - SUPDIPR” on page 194.
ERR_C - Non-Recovered Communication:
When set to one, this bit indicates that there is no signal detected on the PHY receive path (RX). This
may occur from a faulty interconnect or the device has been removed. This bit is cleared by writing a 1
to it.
The default value after reset is 0₂. After reset, when a signal is not detected on the receive path (RX
pair), the value will change to 1₂. After detecting a signal on the receive line, this bit will then change to
0₂.
ERR_T - Non-Recovered Transient Data Integrity Error:
This bit indicates that either a CRC error, disparity error, or the receipt of an R_ERR primitive occurred
in response to a Data FIS. This bit is cleared by writing a 1 to it. This bit is reported as an interrupt on bit
5, 13, 21, and 29 of the SATA Interrupt Pending register for SATA ports 0, 1, 2, and 3 respectively. Refer
to Table 116, “SU PCI DPA Interrupt Pending Register - SUPDIPR” on page 194.
Reserved
ERR_M - Recovered Communications Error:
This bit indicates that the PHY went from not ready-to-ready. This bit shall remain cleared when the
PHY was not detected as ready during the initialization process. When the PHY goes ready after
initialization, this bit shall transition to 1. This bit is cleared by writing a 1 to it. This bit is reported as an
interrupt on bit 1, 9, 17, and 25 of the SATA Interrupt Pending register for SATA ports 0, 1, 2, and 3
respectively. Refer to Table 116, “SU PCI DPA Interrupt Pending Register - SUPDIPR” on page 194.
The default value after reset is 0₂, for example the PHY will not be ready. When the PHY becomes
ready as part of the initialization sequence, the value will change to 1₂.
ERR_I - Reserved, not implemented.
Developer’s Manual
April 2004
99