EW31244SL7QV Datasheet, PDF (10/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Tables
1 Reference Documents ................................................................................................................ 15
2 Terms and Definitions................................................................................................................. 18
3 PCI Commands Supported in PCI IDE Mode ............................................................................. 23
4 PCI Commands Supported in DPA Mode .................................................................................. 24
5 DPA Mode Interface Features .................................................................................................... 27
6 BAR Register usage in M/S and DPA Modes............................................................................. 28
7 Normal Voltage Mode ................................................................................................................. 29
8 Extended Voltage Mode ............................................................................................................. 29
9 Serial EEPROM Interface Pins ................................................................................................... 33
10 SCLK Frequency ........................................................................................................................ 33
11 Serial EEPROM Commands ...................................................................................................... 33
12 Block Write Protect Bits .............................................................................................................. 34
13 Byte Enables on ROM Memory Reads....................................................................................... 36
14 Status Register Format (Refer to Atmel* AT25F1024 Datasheet).............................................. 38
15 Write and Read Command Types .............................................................................................. 44
16 PCI Byte Enables on Read and Write Operations ...................................................................... 44
17 SPI Command ............................................................................................................................ 45
18 SPI Control ................................................................................................................................. 45
19 SPI Status................................................................................................................................... 45
20 SPI Data Register - Address 94h ............................................................................................... 46
21 Interrupt /Activity Status Combinations....................................................................................... 58
22 PCI-X Bus Efficiency for Reads .................................................................................................. 60
23 PCI-X Bus Efficiency for Writes .................................................................................................. 60
24 Read Transfer Rate on PCI-X Bus ............................................................................................. 61
25 Write Transfer Rate on PCI-X Bus ............................................................................................. 61
26 SATA Port Register Mapping in Native PCI IDE Mode .............................................................. 67
27 SATA Superset Registers for SATA Port 0 in DPA Mode .......................................................... 73
28 28-Bit LBA Address Bit Layout in PCI IDE Mode ....................................................................... 75
29 48-Bit LBA Address Bit Layout ................................................................................................... 75
30 48-Bit Address Loading Sequence ............................................................................................. 75
31 28-Bit LBA Address Bit Layout in DPA Mode ............................................................................. 76
32 48-Bit LBA Address Bit Layout in DPA Mode ............................................................................. 76
33 31244 Controller Error Reporting Summary - PCI Interface ...................................................... 95
34 31244 Controller Serial ATA Protocol and Bus Error Conditions ............................................... 98
35 SATA Unit PCI Configuration Space Registers ........................................................................ 106
38 SATA DMA Registers in PCI IDE Mode ................................................................................... 108
36 SATA Command Block Registers in PCI IDE Mode ................................................................. 108
37 SATA Control Block Registers in PCI IDE Mode ...................................................................... 108
39 SU Vendor ID Register - SUVID ............................................................................................... 109
40 SU Device ID Register - SUDID ............................................................................................... 110
41 SU Command Register - SUCMD ............................................................................................ 111
42 SU Status Register - SUSR ...................................................................................................... 112
43 SU Revision ID Register - SURID ............................................................................................ 113
44 SU Class Code Register - SUCCR........................................................................................... 114
45 SU Cacheline Size Register - SUCLSR ................................................................................... 115
46 SU Latency Timer Register - SULT .......................................................................................... 116
47 SU Header Type Register - SUHTR ......................................................................................... 117
48 SU BIST Register - SUBISTR .................................................................................................. 118
49 SU Base Address Register 0 - SUBAR0 .................................................................................. 119
10
April 2004
Developer’s Manual