EW31244SL7QV Datasheet, PDF (231/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.12.7 SU PCI DPA BIST Errors Register - SUPDBER
Table 141.
The SU PCI DPA BIST Errors Register is a 32-bit register. This register is used during far-end
loopback testing. This register is updated/incremented each time an error is detected.
SU PCI DPA BIST Errors Register - SUPDBER
PCI
Attributes
31
28
24
20
16
12
8
4
0
ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro
PCI IDE Mode Offset
= 048H,
DPA Mode Offset
Port 0 = 348H, Port 1 = 548H
Port 2 = 748H, Port 3 = 948H
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Bit
31:16
15:00
Default
0000H
0000H
Description
Reserved
BIST Errors. This register contains the number of errors that occurred since the last time the BIST FIS
Control and Status register bit 25 was set. This register may count up to FFFFH - only 16-bit is
implemented. This register will not rollover after a count of FFFFH is reached. For example, the counter
will stop when a value of FFFFH is reached.
Developer’s Manual
April 2004
231