EW31244SL7QV Datasheet, PDF (4/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
4 Functional Blocks .......................................................................................................................... 48
4.1 Serial ATA........................................................................................................................... 48
4.1.1 Out-of-Band Signaling ........................................................................................... 50
4.2 Operational Blocks.............................................................................................................. 53
4.2.1 Serial Engine ......................................................................................................... 54
4.2.2 Register Interface .................................................................................................. 54
4.2.3 DMA Controller ...................................................................................................... 55
4.2.3.1 DMA Operation ...................................................................................... 57
4.2.3.2 Data Synchronization............................................................................. 58
4.2.3.3 DMA Error Conditions ............................................................................ 59
4.2.3.4 DMA Throughput.................................................................................... 60
4.2.4 Programmed I/O (PIO)........................................................................................... 62
4.2.5 Serial ATA II Native Command Queuing ............................................................... 63
4.2.5.1 Race-free Status Return Mechanism..................................................... 64
4.2.5.2 Interrupt Aggregation ............................................................................. 64
4.2.5.3 First Party DMA (FPDMA)...................................................................... 65
5 Programming Interface .................................................................................................................. 66
5.1 PCI IDE Mode..................................................................................................................... 67
5.1.1 Native-PCI Mode ................................................................................................... 67
5.2 Direct Port Access Mode .................................................................................................... 69
5.2.1 Common Serial ATA Port Registers ...................................................................... 70
5.2.2 Command Block Registers .................................................................................... 70
5.2.3 Control Block Registers ......................................................................................... 71
5.2.4 DMA Controller Registers ...................................................................................... 71
5.2.5 SATA Superset Registers...................................................................................... 72
5.3 ATA Command Processing ................................................................................................ 74
5.3.1 LBA Addressing in PCI IDE Mode ......................................................................... 75
5.3.2 LBA Addressing in DPA Mode............................................................................... 76
5.4 Reset Initialization............................................................................................................... 77
5.5 Serial ATA BIST.................................................................................................................. 79
5.5.1 Loopback Mode Testing ........................................................................................ 81
5.5.2 Transmit-Only Mode Testing ................................................................................. 82
5.6 PCI Bus Error Conditions.................................................................................................... 83
5.6.1 Address and Attribute Parity Errors on the PCI Interface ...................................... 83
5.6.2 Data Parity Errors on the PCI Interface ................................................................. 84
5.6.2.1 Outbound Read Request Data Parity Errors.......................................... 84
5.6.2.1.1 Immediate Data Transfer ................................................................ 84
5.6.2.1.2 Split Response Termination ............................................................ 85
5.6.2.2 Outbound Write Request Data Parity Errors.......................................... 86
5.6.2.2.1 Outbound Writes that are Not MSI (Message Signaled Interrupts). 86
5.6.2.2.2 MSI Outbound Writes...................................................................... 86
5.6.2.3 Inbound Read Request Data Parity Errors ............................................ 87
5.6.2.3.1 Immediate Data Transfer ................................................................ 87
5.6.2.4 Inbound Write Request Data Parity Errors............................................. 87
5.6.2.5 Outbound Read Completion Data Parity Errors..................................... 87
5.6.2.6 Split Completion Messages ................................................................... 88
5.6.3 Master Aborts on the PCI Interface ....................................................................... 89
5.6.3.1 Master-Aborts Signaled by Intel^® 31244 PCI-X to Serial ATA Controller
as an Initiator ......................................................................................... 89
5.6.3.1.1 Master Aborts for Outbound Read or Write Request ...................... 89
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April 2004
Developer’s Manual