EW31244SL7QV Datasheet, PDF (141/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.2.33 SU Interrupt Status Register SUISR
Table 71.
This register reports interrupts generated by the SATA ports. Software must clear any pending
interrupt at the appropriate sources. The IDE interrupts (bits 31, 23, 15, 7) are cleared by reading
the SATA Port Command Block Status register. Other pending interrupts in this register are
generated by the Superset Error registers and must be cleared by writing 1s to the Superset Error
registers. These registers located in configuration space for PCI IDE mode and in the memory
space for DPA mode.
SU Interrupt Status Register - SUISR
31
28
24
20
16
12
8
4
0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bit
31:24
23:16
15:8
7
6
5
4
3
2
1
0
31:00
PCI Configuration Address Offset
A8-AB PCI IDE
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Default
0
0
0
0
0
0
0
0
0
0
0
0000_0000
PCI IDE Description
Port 4 Interrupt Status. Same as bits 7:0 corresponding to Port 4
Port 3 Interrupt Status. Same as bits 7:0 corresponding to Port 3
Port 2 Interrupt Status. Same as bits 7:0 corresponding to Port 3
Port 1 ATA Interrupt
Port 1 CRC Error. This is the latched CRC error from the previous data transfer.
Port 1 Data Integrity Error. A CRC or disparity error was detected by the host, or an RERR was
returned by the device in response to a data FIS transfer.
Port 1 Unrecognized FIS Reception. An unrecognized FIS type was received.
Port 1 RERR Received. An RERR was received in response to a data transfer.
Port 1 FIFO Error. A FIFO error occurred during a data FIS transfer
Port 1 PHY went from Not-Ready to Ready steady state. The PHY became ready and OOB was
completed.
Port 1 PHY Ready Change-Of-State. The PHY went from Ready to Not Ready or from Not-Read to
Ready.
PCI DPA Mode Description
Reserved - Note: Bits are Read Only in DPA mode
Developer’s Manual
April 2004
141