EW31244SL7QV Datasheet, PDF (198/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
Table 116. SU PCI DPA Interrupt Pending Register - SUPDIPR (Sheet 4 of 5)
PCI
Attributes
31
28
24
20
16
12
8
4
0
ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro
DPA Mode BAR0 Offset
000H
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Bit
Default
Description
SATA Port 1 PHY Change State Interrupt - When set, the PHY either went from READY to
NOT-READY, or from NOT-READY to READY. The source of this interrupt is from bit 16 (DIAG_N) of
the SError register. This interrupt is cleared by writing a 1 to bit 16 of the SError register. Refer to
08
0₂
Section 5.10.12.2, “SU PCI DPA SATA SError Register - SUPDSSER” on page 222.
The default value after reset is 0₂, for example the PHY will not be ready. When the PHY becomes
ready (state change from not-ready to ready) as part of the initialization sequence, the value will change
to 1₂.
SATA Port 0 IDE Interrupt - When set, this bit indicates that the SATA device generated an interrupt.
07
0₂
This is the same as PCI IDE compatible interrupt. The source of this interrupt is based on the setting of
the “I” bit in the Device-to-Host Register FIS. This interrupt is cleared by reading the taskfile Status
register.
SATA Port 0 CRC Error Detect Interrupt - When set, this bit indicates that a CRC error was detected on
06
0₂
a previous data transfer. The source of this interrupt is from bit 21 (DIAG_C) of the SError register. This
interrupt is cleared by writing a 1 to bit 21 of the SError register. Refer to Section 5.10.12.2, “SU PCI
DPA SATA SError Register - SUPDSSER” on page 222.
SATA Port 0 Data Integrity Interrupt - When set, this bit indicates that a CRC, disparity error was
detected by the host, or an R_ERR primitive was returned by the device in response to a Data FIS
05
0₂
transfer. The source of this interrupt is from bit 8 (ERR_T) of the SError register. This interrupt is cleared
by writing a 1 to bit 8 of the SError register. Refer to Section 5.10.12.2, “SU PCI DPA SATA SError
Register - SUPDSSER” on page 222.
SATA Port 0 Unrecognized FIS Reception Interrupt - When set, this bit indicates that an unsupported
04
0₂
FIS was detected. The source of this interrupt is from bit 10 (ERR_P) of the SError register. This
interrupt is cleared by writing a 1 to bit 10 of the SError register. Refer to Section 5.10.12.2, “SU PCI
DPA SATA SError Register - SUPDSSER” on page 222.
SATA Port 0 R_ERR Received Interrupt - When set, this bit indicates that an R_ERR primitive was
03
0₂
received during a Data FIS transfer. The source of this interrupt is from bit 22 (DIAG_H) of the SError
register. This interrupt is cleared by writing a 1 to bit 22 of the SError register. Refer to
Section 5.10.12.2, “SU PCI DPA SATA SError Register - SUPDSSER” on page 222.
SATA Port 0 FIFO Error Interrupt - When set, a FIFO error occurred during a Data FIS transfer. The
02
0₂
source of this interrupt is from bit 11 (ERR_E) of the SError register. This interrupt is cleared by writing
a 1 to bit 11 of the SError register. Refer to Section 5.10.12.2, “SU PCI DPA SATA SError Register -
SUPDSSER” on page 222.
SATA Port 0 PHY Ready Interrupt - When set, a SATA Port 0 PHY became READY from NOT READY.
OOB is done. The source of this interrupt is from bit 1 (ERR_M) of the SError register. This interrupt is
cleared by writing a 1 to bit 1 of the SError register. Refer to Section 5.10.12.2, “SU PCI DPA SATA
01
0₂
SError Register - SUPDSSER” on page 222.
The default value after reset is 0₂, for example the PHY will not be ready. When the PHY becomes
ready as part of the initialization sequence, the value will change to 1₂.
198
April 2004
Developer’s Manual