EW31244SL7QV Datasheet, PDF (181/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.5.4
.
Table 109.
SU IDE Channel 1 DMA Command Register - SUICDCR1
The SU IDE Channel 1 DMA Command Register enables/disables the DMA engine (bus master
capability) and also provides direction control for DMA transfers.
SU IDE Channel 1 DMA Command Register - SUICDCR1
PCI
Attributes
15
12
8
4
0
rv rv rv rv rv rv ro ro rv rv rv rv rw rv rv rw
Bit
15:10
09
08
07:04
03
02:01
00
PCI IDE Mode BAR4 Offset
= 08H
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Default
00H
0₂
0₂
0H
0₂
00₂
0₂
Description
Reserved
First Party DMA Direction:
0 = From Device to Host
1 = From Host to Device
First Party DMA Active:
0 = Not Active
1 = Active
Reserved
DMA Read/Write Control:
0 = Reads
1 = Writes
This bit must NOT be changed when the DMA is active. While synchronous DMA transfer is in progress,
this bit will be READ ONLY. The bit will return to read/write once the synchronous DMA transfer has
been completed or halted.
Reserved.
Start/Stop DMA Transfer:
0 = Stop
1 = Start
When this bit is set to 1, the DMA operation starts. The controller transfers data between the device and
memory only while this bit is set. Operation may be stopped by writing a 0 to this bit. This results in all
state information being lost (i.e., operation cannot be stop and then resumed).
When this bit is set to 0 while bus master operation is still active (i.e., bit 0 = 1 in the DMA Status
Register) and data transfer has not yet finished (i.e., bit 2 = 0 in the DMA Status Register), the DMA
command is aborted and data transferred from the drive may be discarded by the SATA port rather than
being written to memory. This bit is intended to be set to 0 after the data transfer is completed, as
indicated by either bit 0 or bit 2 set in the DMA Status Register.
Developer’s Manual
April 2004
181