EW31244SL7QV Datasheet, PDF (167/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.3.2
Table 95.
SU IDE Error Register - SUIER
The SU IDE Error Register is an 8-bit read-only register. When the SU IDE Error Register is
written to, instead the SU IDE Features Register is written. The SU IDE Error Register contains
error status for the current command. The content of this register shall be valid when the ERR bit is
set in the SU IDE Status Register - SUISR. The SU IDE Error Register is command dependent and
the bits are defined in the AT Attachment with Packet Interface-6 (ATA/ATAPI-6) Specification.
SU IDE Error Register - SUIER
PCI
Attributes
7
4
0
ro ro ro ro ro ro ro ro
PCI IDE Mode BAR0/BAR2 Offset
= 01H
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Bit
Default
Description
07:00
Device
Dependent ^a
The bits in this register are command dependent. The bits are only valid when the ERR bit (bit 0) in the
SU IDE Status Register - SUISR is set. Refer to the AT Attachment with Packet Interface-6
(ATA/ATAPI-6) Specification.
a. After a hardware reset, software reset, or an EXECUTE DEVICE DIAGNOSTIC command, the device will return a diagnostic code. The diagnostic
code is device dependent. AT Attachment with Packet Interface-6 (ATA/ATAPI-6) Specification.
Developer’s Manual
April 2004
167