EW31244SL7QV Datasheet, PDF (6/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
5.10.2.28 SPI Status Register - SPISTATR......................................................... 136
5.10.2.29 SPI Data Register - SPIDATR ............................................................. 137
5.10.2.30 SU Extended Control and Status Register 0 - SUECSR0 ................... 138
5.10.2.31 SU DMA Control Status Register- SUDCSCR..................................... 139
5.10.2.32 SU Dummy Register SUDR ................................................................. 140
5.10.2.33 SU Interrupt Status Register SUISR .................................................... 141
5.10.2.34 SU Interrupt Mask Register SUIMR ..................................................... 142
5.10.2.35 SU Transaction Control SUTCR .......................................................... 143
5.10.2.36 SU Target Split Completion Message Enable Register SUTSCMER .. 144
5.10.2.37 SU Target Delayed/Split Request Pending Register SUDRPR ........... 145
5.10.2.38 SU Transaction Control 2 Register SUTC2R....................................... 146
5.10.2.39 SU Master Deferred/Split Sequence Pending Register - SUMDSPR .. 148
5.10.2.40 SU Master Split Completion Message Received
with Error Message Register - SUMSCMREMR.................................. 149
5.10.2.41 SU Arbiter Control - SUACR ................................................................ 150
5.10.2.42 SU PCI-X Capability Identifier Register - SUPCI-X_Cap_ID ............... 151
5.10.2.43 SU PCI-X Next Item Pointer Register - SUPCI-X_Next_Item_Ptr ....... 152
5.10.2.44 SU PCI-X Command Register - SUPCIXCMD..................................... 153
5.10.2.45 SU PCI-X Status Register - SUPCIXSR .............................................. 154
5.10.2.46 SU PM Capability Identifier Register - SUPM_Cap_ID........................ 156
5.10.2.47 SU PM Next Item Pointer Register - SUPM_Next_Item_Ptr ................ 157
5.10.2.48 SU Power Management Capabilities Register - SUPMCR .................. 158
5.10.2.49 SU Power Management Control/Status Register - SUPMCSR ........... 159
5.10.2.50 SU MSI Capability Identifier Register - SUMSI_Cap_ID...................... 160
5.10.2.51 SU MSI Next Item Pointer Register - SUMSI_Next_Ptr....................... 161
5.10.2.52 SU MSI Message Control Register - SUMSI_Message_Control ......... 162
5.10.2.53 SU MSI Message Address Register - SUMSI_Message_Address ...... 163
5.10.2.54 SU MSI Message Upper Address Register -
SUMSI_Message_Upper_Address ...................................................... 164
5.10.2.55 SU MSI Message Data Register- SUMSI_Message_Data .................. 165
5.10.3 SU PCI IDE Mode Command Block Registers .................................................... 166
5.10.3.1 SU IDE Data Port Register - SUIDR .................................................... 166
5.10.3.2 SU IDE Error Register - SUIER ........................................................... 167
5.10.3.3 SU IDE Features Register - SUIFR ..................................................... 168
5.10.3.4 SU IDE Sector Count Register - SUISCR............................................ 169
5.10.3.5 SU IDE Sector Number Register - SUISNR......................................... 170
5.10.3.6 SU IDE Cylinder Low Register - SUICLR ............................................ 171
5.10.3.7 SU IDE Cylinder High Register - SUICHR ........................................... 172
5.10.3.8 SU IDE Device/Head Register - SUIDR............................................... 173
5.10.3.9 SU IDE Status Register - SUISR ......................................................... 174
5.10.3.10 SU IDE Command Register - SUICR................................................... 175
5.10.4 SU PCI IDE Mode Control Block Registers ......................................................... 176
5.10.4.1 SU IDE Device Control Register - SUIDCR ......................................... 176
5.10.4.2 SU IDE Alternate Status Register - SUIASR ....................................... 177
5.10.5 SU PCI IDE Mode DMA Registers....................................................................... 178
5.10.5.1 SU IDE Channel 0 DMA Command Register - SUICDCR0 ................. 178
5.10.5.2 SU IDE Channel 0 DMA Status Register - SUICDSR0........................ 179
5.10.5.3 SU IDE Channel 0 DMA Descriptor Table
Pointer Register - SUICDDTPR0 ......................................................... 180
5.10.5.4 SU IDE Channel 1 DMA Command Register - SUICDCR1 ................. 181
5.10.5.5 SU IDE Channel 1 DMA Status Register - SUICDSR1........................ 182
5.10.5.6 SU IDE Channel 1 DMA Descriptor Table
Pointer Register - SUICDDTPR1 ......................................................... 183
5.10.6 SU PCI DPA Mode Registers .............................................................................. 184
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April 2004
Developer’s Manual