EW31244SL7QV Datasheet, PDF (166/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.3
5.10.3.1
.
Table 94.
SU PCI IDE Mode Command Block Registers
This section defines the Command Block Registers when in PCI IDE mode.
SU IDE Data Port Register - SUIDR
The SU IDE Data Port Register is a 16-bit read/write register and is used to transfer data during
Programmed I/O (PIO) mode reads/writes. On the GD31244 controller, the Data Port register may
also be read or written as a 32-bit Data Port. The GD31244 controller internally breaks the 32-bit
transaction into two back-to-back 16-bit transactions. It is recommended that the Data Port register
is always accessed in either 16-bit or 32-bit quantity for a given PIO sequence. Refer to the AT
Attachment with Packet Interface-6 (ATA/ATAPI-6) Specification.
SU IDE Data Port Register - SUIDR
PCI
Attributes
15
12
8
4
0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bit
15:00
PCI IDE Mode BAR0/BAR2 Offset
=00H
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Default
0000H
Description
Data Port - This register is used to transfer data during PIO reads and writes. This register shall be
accessed only when the DRQ bit in the status register, SU IDE Status Register - SUISR, is set.
166
April 2004
Developer’s Manual