EW31244SL7QV Datasheet, PDF (70/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.2.1 Common Serial ATA Port Registers
Figure 24.
This section defines the registers that are common to all the Serial ATA ports for the SATA Unit.
Figure 24 shows the registers mapping.
Common Serial ATA Port Registers
31
Serial ATA Unit Interrupt Pending Register
Serial ATA Unit Interrupt Mask Register
Reserved
0 Offset
000H
004H
008H - 1FFH
5.2.2 Command Block Registers
Figure 25.
The Command Block Registers are used to issue ATA commands to the device. The Command
Register must be written after the other registers in the Command Block are loaded, because the
rest of the registers are parameters based on the command. The structure of the command block is
shown in Figure 25. The Command Block Registers are memory-mapped when in the Direct Port
Access mode. When in the PCI IDE mode, the Command Block Registers are I/O-mapped in the
PCI I/O space. Figure 25 shows the Command Block Registers mapping when in the Direct Port
Access mode (DPA) for SATA Port 0. Refer to Section , “The SATA Unit may be set up during
system reset to execute in one of the following modes. Each mode provides a different
programming interface. The DPA_MODE# external strap signal is sampled during the rising edge
of PCI reset, to determine the operation mode.” on page 62 for further details on the mapping of
these registers.
Command Block Registers for SATA Port 0
31
Data Port Register
Features/Error Register
Sector Count Register
Sector Number Register
Cylinder Low Register
Cylinder High Register
Device/Head Register
Command/Status Register
0 Offset
200H
204H
208H
20CH
210H
214H
218H
21CH
70
April 2004
Developer’s Manual