EW31244SL7QV Datasheet, PDF (112/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.2.4
Table 42.
SU Status Register - SUSR
The SU Status Register bits adhere to the PCI Local Bus Specification, Revision 2.2 definitions.
The read/clear bits may only be set by internal hardware and cleared by either a reset condition or
by writing a 1₂ to the register.
SU Status Register - SUSR
PCI
Attributes
15
12
8
4
0
rc rc rc rc rc ro ro rc ro ro ro ro rv rv rv rv
PCI Configuration Address Offset
06H - 07H
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Bit
Default
Description
15
14
13
12
11
10:09
08
07
06
05
04
03:00
Detected Parity Error - set when a parity error is detected in data received by the SATA Unit on the PCI bus
even when the SUCMD register Parity Error Response bit is cleared. Set under the following conditions:
0₂
• Write Data Parity Error when the SATA Unit is a target (inbound write).
• Read Data Parity Error when the SATA Unit is a requester (outbound read).
• Any Address or Attribute (PCI-X Only) Parity Error on Bus (including one generated by SATA Unit).
0₂
SERR# Asserted - set when SERR# is asserted on the PCI bus by the SATA Unit.
Master Abort - set when a transaction initiated by the SATA Unit PCI master interface, ends in a
0₂
Master-Abort or when the SATA Unit receives a Master Abort Split Completion Error Message in PCI-X
mode.
Target Abort (master) - set when a transaction initiated by the SATA Unit PCI master interface, ends in a
0₂
target abort or when the SATA Unit receives a Target Abort Split Completion Error Message in PCI-X
mode.
0₂
Target Abort (target) - set when the SATA Unit interface, acting as a target, terminates the transaction on
the PCI bus with a target abort.
DEVSEL# Timing - These bits are read-only and define the slowest DEVSEL# timing for a target device
in Conventional PCI Mode regardless of the operating mode (except configuration accesses).
00₂ = Fast
01₂
01₂ = Medium
10₂ = Slow
11₂ = Reserved
The SATA Unit interface uses Medium timing.
Master Parity Error - The SATA Unit interface sets this bit under the following conditions:
0₂
• The SATA Unit asserted PERR# itself or the SATA Unit observed PERR# asserted.
• And the SATA Unit acted as the requester for the operation in which the error occurred.
• And the SUCMD register Parity Error Response bit is set
1₂
(Conventional _{Fast Back-to-Back - The SATA Unit interface is capable of accepting fast back-to-back transactions in}
mode) _{Conventional PCI mode when the transactions are not to the same target. Since fast back-to-back}
0₂
transactions do not exist in PCI-X mode, this bit will be forced to 0 in the PCI-X mode.
(PCI-X mode)
0₂
1₂
12
00000₂
UDF Supported - User Definable Features are not supported
66 MHz. Capable - 66 MHz operation is supported.
Capabilities - When set, this function implements extended capabilities.
Reserved.
112
April 2004
Developer’s Manual