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EW31244SL7QV Datasheet, PDF (179/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller
Intel® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.5.2
.
Table 107.
SU IDE Channel 0 DMA Status Register - SUICDSR0
The SU IDE Channel 0 DMA Status Register provides status of the DMA engine.
SU IDE Channel 0 DMA Status Register - SUICDSR0
PCI
Attributes
7
43
0
ro rw rw rv rv rc rc ro
Bit
07
06
05
04:03
02
01
00
PCI IDE Mode BAR4 Offset
= 02H
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Default
02
12
12
002
02
02
02
Description
This bit is hardwired to 0. Simplex only.
Drive 1 DMA Capable: 1 = Drive 1 is capable of DMA transfers. This bit is a software controlled status bit
that indicates DMA device capability and does not affect hardware operation.
Drive 0 DMA Capable: 1 = Drive 0 is capable of DMA transfers. This bit is a software controlled status bit
that indicates DMA device capability and does not affect hardware operation.
Reserved.
Interrupt Status: This bit, when set to a 1, indicates that a device has asserted its interrupt line. When
this is set to 1, all read data from the device has been transferred to memory and all write data has been
transferred to the device. Software sets this bit to a 0 by writing a 1 to it.
DMA Error: This bit is set to 1 under the following conditions while transferring data on the PCI bus.
• Detected a master abort on the PCI bus
• Detected a target abort on the PCI bus
• Detected a parity error on the PCI bus
Software sets this bit to 0 by writing a 1 to it.
DMA Active: The GD31244 sets this bit to 1 when bit 0 in the SU IDE Channel 0 DMA Command
Register is set to 1. Refer to Table 106, “SU IDE Channel 0 DMA Command Register - SUICDCR0” on
page 178. The GD31244 sets this bit to 0 when the last transfer is performed (where EOT for that
descriptor is set). The GD31244 also sets this bit to 0 when bit 0 of the SU IDE Channel 0 DMA
Command Register is set to 0. When this bit is read as a 0, all data transferred from the drive during the
previous bus master command is visible in memory, unless the DMA command was aborted.
Developer’s Manual
April 2004
179