EW31244SL7QV Datasheet, PDF (40/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Serial EEPROM
3.1.6 Sector Erase (SECT_ERASE) Command
Figure 11.
Before an EEPROM byte may be reprogrammed, the sector that contains the byte must be erased.
In order to erase the EEPROM, two separate commands must be executed. First, the device must be
write enabled through the WREN command, then the SECT_ERASE command may be executed.
The SECT_ERASE command is internally controlled; it will automatically be timed to completion.
During this time, all commands will be ignored, except RDSR command. The EEPROM will
automatically return to the write disable state at the completion of the SECT_ERASE cycle.
The SECT_ERASE command erases every byte in the selected sector if the sector is not
Write-Protected. The EEPROM Sector address (bits 16 & 15) is determined by two bits in the SPI
Command Register at offset 91h: spi_sect_addr1 (mapped to bit 16) and spi_sect_addr0 (mapped
to bit 15). These bits form the uppermost bits of the memory address and split the memory into the
four sectors. Address bits 23-17 are LOW. The sector erase (SECT_ERASE) operation is shown in
Figure 11.
Sector Erase (SECT_ERASE) Operation
SCS#
SCLK
SDO
0 4 8 12 16 20 24 28 32 36 40 44 48 52 54 56
00000011
23-bit Address
SDI
Hi -Z
Byte 0 Byte 1 Byte 2 Byte 3
Hi -Z
76543210 76543210 76543210 76543210
To issue a SECT_ERASE command:
1. Issue a WREN command as described in Section 3.1.5.
2. Issue a RDSR command to read that the RDY# bit is LOW and the WEN bit is HIGH in the
EEPROM’s Status Register to ensure that the EEPROM is ready to receive a write command.
3. When RDY# is not low, continue issuing RDSR commands until RDY# becomes low.
4. Issue a SECT_ERASE command by an 8-bit write of 52h to the SPI Command Register at
offset 90h.
40
April 2004
Developer’s Manual