EW31244SL7QV Datasheet, PDF (201/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
Table 117. SU PCI DPA Interrupt Mask Register - SUPDIMR (Sheet 2 of 3)
PCI
Attributes
31
28
24
20
16
12
8
4
0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
DPA Mode BAR0 Offset
004H
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Bit
Default
Description
SATA Port 2 Data Integrity Interrupt Mask Bit.
21
0₂
0 = Masked
1 = Not Masked
SATA Port 2 Unrecognized FIS Reception Interrupt Mask Bit.
20
0₂
0 = Masked
1 = Not Masked
SATA Port 2 R_ERR Primitive Received Interrupt Mask Bit.
19
0₂
0 = Masked
1 = Not Masked
SATA Port 2 FIFO Error Interrupt Mask Bit.
18
0₂
0 = Masked
1 = Not Masked
SATA Port 2 PHY Ready Interrupt Mask Bit.
17
0₂
0 = Masked
1 = Not Masked
SATA Port 2 PHY Change State Interrupt Mask Bit.
16
0₂
0 = Masked
1 = Not Masked
SATA Port 1 IDE Interrupt Mask Bit.
15
1₂
0 = Masked
1 = Not Masked
SATA Port 1 Signal Detect Interrupt Mask Bit.
14
0₂
0 = Masked
1 = Not Masked
SATA Port 1 Data Integrity Interrupt Mask Bit.
13
0₂
0 = Masked
1 = Not Masked
SATA Port 1 Unrecognized FIS Reception Interrupt Mask Bit.
12
0₂
0 = Masked
1 = Not Masked
SATA Port 1 R_ERR Primitive Received Interrupt Mask Bit.
11
0₂
0 = Masked
1 = Not Masked
SATA Port 1 FIFO Error Interrupt Mask Bit.
10
0₂
0 = Masked
1 = Not Masked
Developer’s Manual
April 2004
201