EW31244SL7QV Datasheet, PDF (218/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.11.4 SU PCI DPA DMA Status Register - SUPDDSR
.
Table 133.
The SU PCI DPA DMA Status Register provides status of the DMA engine.
SU PCI DPA DMA Status Register - SUPDDSR
PCI
Attributes
7
43
0
ro rv rw rv rv rc rc ro
Bit
07
06
05
04:03
02
01
00
DPA Mode BAR0 Offset
Port 0 = 272H, Port 1 = 472H
Port 2 = 672H, Port 3 = 872H
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Default
0₂
0₂
1₂
00₂
0₂
0₂
0₂
Description
This bit is hardwired to 0. Simplex only.
Reserved.
DMA Capable: 1 = Capable of DMA transfers. This bit is a software controlled status bit that indicates
DMA device capability and does not affect hardware operation.
Reserved.
Interrupt Status: This bit, when set to a 1, indicates when a device has asserted its interrupt line. When
this bit is set to 1, all read data from the device has been transferred to memory and all write data has
been transferred to the device. Software sets this bit to a 0 by writing a 1 to it.
DMA Error: This bit is set to 1 under the following conditions while transferring data on the PCI bus.
• Detected a master abort on the PCI bus
• Detected a target abort on the PCI bus
• Detected a parity error on the PCI bus
Software sets this bit to 0 by writing a 1 to it.
DMA Active: The GD31244 controller sets this bit to 1 when bit 0 in the SU PCI DPA DMA Command
Register is set to 1. Refer to Section 5.10.11.3, “SU PCI DPA DMA Command Register - SUPDDCMDR”
on page 217. The GD31244 controller sets this bit to 0 when the last transfer is performed (where EOT
for that descriptor is set). The GD31244 controller also sets this bit to 0 when bit 0 of the IDE Channel 0
DMA Command Register is set to 0. When this bit is read as a 0, all data transferred from the drive
during the previous bus master command is visible in memory, unless the DMA command was aborted.
218
April 2004
Developer’s Manual