EW31244SL7QV Datasheet, PDF (108/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
Table 36.
Table 37.
s
Table 38.
SATA Command Block Registers in PCI IDE Mode
Register Name
Bits
Access
BAR 0/2 + Offset
SU IDE Data Port Register - SUIDR
16
Read/Write
00H
SU IDE Error Register - SUIER
8
Read Only
01H
SU IDE Features Register - SUIFR
8
Write Only
01H
SU IDE Sector Count Register - SUISCR
8
Read/Write
02H
SU IDE Sector Number Register - SUISNR
8
Read/Write
03H
SU IDE Cylinder Low Register - SUICLR
8
Read/Write
04H
SU IDE Cylinder High Register - SUICHR
8
Read/Write
05H
SU IDE Device/Head Register - SUIDHR
8
Read/Write
06H
SU IDE Status Register - SUISR
8
Write Only
07H
SU IDE Command Register - SUICR
8
Read Only
07H
NOTE: In Native-PCI mode, the offset is relative to the PCI Base Address Registers at offset 10H and 18H in
the PCI Configuration Space. Base Address Register at offset 10H points to Channel 0. And Base
Address Register at offset 18H points to Channel 1.
SATA Control Block Registers in PCI IDE Mode
Register Name
Bits
Access
BAR 0/2 + Offset
Reserved.
8
00H
Reserved.
8
01H
SU IDE Device Control Register - SUIDCR
8
Write Only
02H
SU IDE Alternate Status Register - SUIASR
8
Read Only
02H
Reserved.
8
03H
NOTE: In Native-PCI mode, the offset is relative to the PCI Base Address Registers at offset 14H and 1CH in
the PCI Configuration Space. Base Address Register at offset 14H points to Channel 0. And Base
Address Register at offset 1CH points to Channel 1.
SATA DMA Registers in PCI IDE Mode
Register Name
Bits
Offset
SU IDE Channel 0 DMA Command Register - SUICDCR0
8
00H
Reserved
8
01H
SU IDE Channel 0 DMA Status Register - SUICDSR0
8
02H
Reserved
8
03H
SU IDE Channel 0 DMA Descriptor Table Pointer Register -
SUICDDTPR0
32
04H
SU IDE Channel 1 DMA Command Register - SUICDCR1
8
08H
Reserved
8
09H
SU IDE Channel 1 DMA Status Register - SUICDSR1
8
0AH
Reserved
8
0BH
SU IDE Channel 1 DMA Descriptor Table Pointer Register -
SUICDDTPR1
32
0CH
NOTE: The offset is relative to the PCI Base Address Register at offset 20H in the PCI Configuration Space.
108
April 2004
Developer’s Manual