EW31244SL7QV Datasheet, PDF (193/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.7.2
Table 115.
SU PCI DPA Upper Base Address Register 0 - SUPDUBAR0
This SU PCI DPA Upper Base Address Register (SUPDUBAR0) contains the upper base address
when decoding PCI addresses beyond 4 Gbytes. Together with the SU PCI DPA Base Address
Register 0 (SUPDBAR0), this register defines the actual location the SATA Unit responds to when
addressed from the PCI bus for addresses > 4 Gbytes (for DACs).
The programmed value within the base address register must comply with the PCI programming
requirements for address alignment. Refer to the PCI Local Bus Specification, Revision 2.2 for
additional information on programming base address registers.
SU PCI DPA Upper Base Address Register 0 - SUPDUBAR0
PCI
Attributes
31
28
24
20
16
12
8
4
0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
PCI Configuration Address Offset
14H - 17H
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Bit
31:00
Default
Description
0000_0000H
Upper Base Address 0 - Together with Base Address 0 these bits define the actual location the SATA
Unit is to respond to when addressed from the PCI bus for addresses > 4 Gbytes.
Developer’s Manual
April 2004
193