EW31244SL7QV Datasheet, PDF (106/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
Table 35. SATA Unit PCI Configuration Space Registers (Sheet 1 of 2)
Register Name
SU Vendor ID Register - SUVID
SU Device ID Register - SUDID
SU Command Register - SUCMD
SU Status Register - SUSR
SU Revision ID Register - SURID
SU Class Code Register - SUCCR
SU Cacheline Size Register - SUCLSR
SU Latency Timer Register - SULT
SU Header Type Register - SUHTR
SU BIST Register - SUBISTR
SU Base Address Register 0 - SUBAR0
SU Base Address Register 1 - SUBAR1
SU Base Address Register 2 - SUBAR2
SU Base Address Register 3 - SUBAR3
SU Base Address Register 4 - SUBAR4
SU Base Address Register 5 - SUBAR5
Reserved.
SU Subsystem Vendor ID Register - SUSVIR
SU Subsystem ID Register - SUSIR
SU Expansion ROM Base Address Register - SUEXROMBAR.
SU Capabilities Pointer Register - SU_Cap_Ptr
Reserved.
Reserved.
SU Interrupt Line Register - SUILR
SU Interrupt Pin Register - SUIPR
SU Minimum Grant Register - SUMGNT
SU Maximum Latency Register - SUMLAT
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Bits
PCI Configuration
Cycle Register #
Offset
16
0
00H
16
0
02H
16
1
04H
16
1
06H
8
2
08H
24
2
09H
8
3
0CH
8
3
0DH
8
3
0EH
8
3
0FH
32
4
10H
32
5
14H
32
6
18H
32
7
1CH
32
8
20H
32
9
24H
32
10
28H
16
11
2CH
16
11
2EH
32
12
30H
8
13
34H
24
13
35H
32
14
38H
8
15
3CH
8
15
3DH
8
15
3EH
8
15
3FH
32
16
40H
32
17
44H
32
18
48H
24
19
4CH
8
19
4FH
32
20
50H
32
21
54H
32
22
58H
32
23
5CH
32
24
60h
32
25
64H
32
26
68H
32
27
6CH
32
28
70H
32
29
74H
32
30
78H
32
31
7CH
32
32
80H
106
April 2004
Developer’s Manual