EW31244SL7QV Datasheet, PDF (37/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Serial EEPROM
3.1.3
Figure 8.
Write Disable (WRDI) Command
To protect the device against inadvertent writes, the WRDI command disables further write
commands. The WRDI command is independent of the status of the WP pin. The write disable
(WRDI) operation is shown in Figure 8.
Write Disable (WRDI) Operation
SCS#
SCLK
SDO
01234567
00000100
SDI
Hi -Z
The WRDI command may only be issued when the EEPROM is ready to accept a new command.
When the device is busy, it cannot accept any new commands except RDSR.
To issue a WRDI command:
1. Issue a RDSR command to read that the RDY# bit is LOW in the EEPROM’s Status Register
to ensure that the EEPROM is ready to receive a new command.
2. When RDY# is not LOW, continue issuing RDSR commands until RDY# becomes LOW.
3. Issue the WRDI command with an 8-bit write of 04h to the SPI Command Register at offset
90h.
Developer’s Manual
April 2004
37