EW31244SL7QV Datasheet, PDF (38/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Serial EEPROM
3.1.4
Figure 9.
Table 14.
Read Status Register (RDSR) Command
The RDSR command reads the EEPROM’s status register. This is the most commonly issued
command since the status register must be polled in order to determine that a previously issued
command is complete and the device is ready to accept a new command. The real-time ready
(RDY#) and write enable (WEN) status bits of the EEPROM may be determined by the RDSR
command. Likewise, the write protect (WPEN) and block protect bits (BP1 and BP0) may also be
read. These three bits are non-volatile memory cells which are set using the WRSR command.
During internal write cycles, all other commands will be ignored except the RDSR command. The
read status (RDSR) operation is shown in Figure 9. The status register format is presented in
Table 14.
Read Status Register (RDSR) Operation
SCS#
SCLK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
SDO
00000101
SDI
Hi -Z
76543210
Hi -Z
WPEN: Write Protect control bit
Reserved
Reserved
Reserved
RDY# - Ready bit
WEN - Write Enable status
BP0 - Block Write Protect bit 0
BP1 - Block Write Protect bit 1
The RDSR command is unique in that it is always serviced by the EEPROM even if a previous
command has yet to complete.
To issue a RDSR command:
1. Issue an 8-bit write of 05h to the SPI Command Register at offset 90h.
2. Read an 8-bit value from the SPI Data register at offset 94h.
Status Register Format (Refer to Atmel* AT25F1024 Datasheet)
Bit
Name
Description
7
WPEN
When HIGH, allows override of the hardware write protect pin.
6-4
Reserved These bits are LOW when the device is not in a write cycle. Write with ‘0’.
These two bits control which sectors of the chip are write protected:
00 - None
3
BP1
01 - Sector 4
2
BP0
10 - Sectors 3 & 4
11 - All sectors
1
WEN
When LOW, the device is write protected. When HIGH, the device is write
enabled.
0
RDY#
When LOW, the device is READY. When HIGH, a write cycle is in progress.
38
April 2004
Developer’s Manual