EW31244SL7QV Datasheet, PDF (132/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.2.24 SU Minimum Grant Register - SUMGNT
SU Minimum Grant Register bit definitions adhere to PCI Local Bus Specification, Revision 2.2.
This register specifies the burst period the device requires in increments of eight PCI clocks.
Table 62.
This register and the SU Maximum Latency register are information-only registers which the
configuration uses to determine how often a bus master typically requires access to the PCI bus and
the duration of a typical transfer when it does acquire the bus. This information is useful in
determining the values to be programmed into the bus master latency timers and in programming
the algorithm to be used by the PCI bus arbiter.
SU Minimum Grant Register - SUMGNT
PCI
Attributes
7
4
0
ro ro ro ro ro ro ro ro
Bit
07:00
PCI Configuration Address Offset
3EH
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Default
10H
Description
Minimum grant specifies, in 0.25 µs increments, the minimum burst period the core needs. The core
does not have any special MIN_GNT requirements. In general, the more channels active, the worse the
bus latency and the shorter the burst cycle.
132
April 2004
Developer’s Manual