EW31244SL7QV Datasheet, PDF (145/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.2.37 SU Target Delayed/Split Request Pending Register SUDRPR
Table 75.
This register indicates if any target/delayed split request sequences are pending.
SU Target Split Completion Message Enable Register- SUTSCMER
31
28
24
20
16
12
8
4
0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw _rw rw rw
PCI Configuration Address Offset
C8-CB
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Bit
Default
Description
31:0
0
Target delayed/split request pending sequences.
Developer’s Manual
April 2004
145