EW31244SL7QV Datasheet, PDF (233/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.12.9 SU PCI DPA Host BIST Data Low Register - SUPDHBDLR
Table 143.
The SU PCI DPA Host BIST Data Low Register is the first 32-bit parameter of the SATA BIST
Activate Host-to-Device FIS. Refer to the Serial ATA Specification.
SU PCI DPA Host BIST Data Low Register - SUPDHBDLR
PCI
Attributes
31
28
24
20
16
12
8
4
0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
PCI IDE Mode Offset
= 050H,
DPA Mode Offset
Port 0 = 350H, Port 1 = 550H
Port 2 = 750H, Port 3 = 950H
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
Bit
31:00
Default
Description
0000_0000H This register contains the data transmitted as BIST FIS DWORD 1.
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Developer’s Manual
April 2004
233