EW31244SL7QV Datasheet, PDF (162/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.2.52 SU MSI Message Control Register - SUMSI_Message_Control
Table 90.
The Message Control Register provides system software control over MSI. After reset, MSI is
disabled. System software is permitted to modify the Message Control register read/write bits and
fields while a device driver is not permitted to modify them.
SU MSI Message Control Register - SUMSI_Message_Control
PCI
Attributes
15
12
8
4
0
rv rv rv rv rv rv rv rv ro rw rw rw ro ro ro rw
Bit
15:8
7
6:4
3:1
0
PCI Configuration Offset
F2H - F3H
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Default
00H
1₂
000₂
010₂
0₂
Description
Reserved
64-bit Address Support - This field is set to 1₂ indicating that the GD31244 controller is capable of
generating a 64-bit message address.
Multiple Message Enable - System software writes to this field to indicate the number of messages
allocated to the GD31244 controller. While, the GD31244 controller requests two messages, it is
possible that system software will only allocate one message. The device hardware is designed to
handle both cases. Note: The maximum value assigned to this field should be 2 or less.
Multiple Message Capable - This field is set to 010₂ indicating that the GD31244 controller may issue up
to four unique interrupt messages. Note: The Host can only program the Multiple Message Enable field
with (0, 1, or 2).
000₂ = 1
001₂ = 2
010₂ = 4
011₂ = 8
100₂ = 16
101₂ = 32
110₂ = Reserved
111₂ = Reserved
MSI Enable - Setting this bit enables the GD31244 controller MSI functionality and disables the use of
the P_INTA# interrupt output for GD31244 controller interrupts.
162
April 2004
Developer’s Manual