EW31244SL7QV Datasheet, PDF (5/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
5.6.3.2 Master-Aborts Signaled by Intel^® 31244 PCI-X to Serial ATA Controller
as a Target ............................................................................................. 90
5.6.3.2.1 Unsupported PCI Commands ......................................................... 90
5.6.3.2.2 PCI IDE Control Block Registers..................................................... 90
5.6.4 Target Aborts on the PCI Interface ........................................................................ 91
5.6.4.1 Target Aborts for Outbound Read Request or Outbound
Write Request ........................................................................................ 91
5.6.4.2 Target-Aborts Signaled by Intel^® 31244 PCI-X to Serial ATA Controller
as a Target ............................................................................................. 92
5.6.4.2.1 Configuration Read and Write ......................................................... 92
5.6.4.2.2 I/O Read and Write .........................................................................92
5.6.4.2.3 Memory Read.................................................................................. 92
5.6.5 Corrupted or Unexpected Split Completions.......................................................... 93
5.6.5.1 Completer Address ................................................................................ 93
5.6.5.2 Completer Attributes ..............................................................................93
5.6.6 SERR# Assertion and Detection............................................................................ 94
5.6.7 PCI Error Summary ............................................................................................... 95
5.7 Serial ATA Bus and Device Error Conditions ..................................................................... 98
5.7.1 Serial ATA Device Error Conditions.......................................................................98
5.7.2 Serial ATA Bus and Protocol Error Conditions ...................................................... 98
5.8 SATA Port Interrupt Generation........................................................................................100
5.9 Message-Signaled Interrupts ............................................................................................ 102
5.9.1 Level-Triggered Versus Edge-Triggered Interrupts .............................................102
5.10 Register Definitions........................................................................................................... 103
5.10.1 PCI IDE Mode Registers...................................................................................... 103
5.10.2 PCI Configuration Registers ................................................................................ 109
5.10.2.1 SU Vendor ID Register - SUVID .......................................................... 109
5.10.2.2 SU Device ID Register - SUDID........................................................... 110
5.10.2.3 SU Command Register - SUCMD........................................................ 111
5.10.2.4 SU Status Register - SUSR ................................................................. 112
5.10.2.5 SU Revision ID Register - SURID ........................................................ 113
5.10.2.6 SU Class Code Register - SUCCR ...................................................... 114
5.10.2.7 SU Cacheline Size Register - SUCLSR ............................................... 115
5.10.2.8 SU Latency Timer Register - SULT ..................................................... 116
5.10.2.9 SU Header Type Register - SUHTR .................................................... 117
5.10.2.10 SU BIST Register - SUBISTR .............................................................. 118
5.10.2.11 SU Base Address Register 0 - SUBAR0.............................................. 119
5.10.2.12 SU Base Address Register 1 - SUBAR1.............................................. 120
5.10.2.13 SU Base Address Register 2 - SUBAR2.............................................. 121
5.10.2.14 SU Base Address Register 3 - SUBAR3.............................................. 122
5.10.2.15 SU Base Address Register 4 - SUBAR4.............................................. 123
5.10.2.16 SU Base Address Register 5 - SUBAR5.............................................. 124
5.10.2.17 SU Subsystem Vendor ID Register - SUSVIR ..................................... 125
5.10.2.18 SU Subsystem ID Register - SUSIR .................................................... 126
5.10.2.19 SU Expansion ROM Base Address Register - SUEXROMBAR .......... 127
5.10.2.20 SU Capabilities Pointer Register - SU_Cap_Ptr .................................. 128
5.10.2.21 SU Expansion ROM Base Address - SUEXROM ................................ 129
5.10.2.22 SU Interrupt Line Register - SUILR...................................................... 130
5.10.2.23 SU Interrupt Pin Register - SUIPR ....................................................... 131
5.10.2.24 SU Minimum Grant Register - SUMGNT .............................................132
5.10.2.25 SU Maximum Latency Register - SUMLAT.......................................... 133
5.10.2.26 SPI Command Register - SPICMDR ................................................... 134
5.10.2.27 SPI Control Register - SPICNTR .........................................................135
Developer’s Manual
April 2004
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