EW31244SL7QV Datasheet, PDF (55/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Functional Blocks
4.2.3 DMA Controller
Several ATA commands use the DMA controller to transfer data. In DPA mode, each SATA port on
the GD31244 controller supports its own DMA controller. This allows each SATA port to transfer
data independent of each other. In PCI IDE mode, each channel (two SATA ports) supports one
DMA controller. Data may be either received or transmitted to the SATA device using the DMA
controller. The programming model provides a simple scatter/gather mechanism allowing large
transfer blocks to be scattered to or gathered from memory. The DMA controller accesses system
memory to read DMA descriptors. The DMA controller uses the DMA Descriptor Table Pointer to
access the descriptors. The descriptor table contains a number of descriptors which describe areas
of memory that are involved in the data transfer.
Figure 20 shows the structure of a descriptor table. The descriptor table is prepared and placed in
memory by software. The descriptor table must be DWORD aligned and must not cross a 64 Kbyte
boundary. Each descriptor is 8 bytes in length. The first DWORD specifies the WORD address of the
data buffer. The lower two bytes of the second DWORD specifies the byte count of the data buffer. A
value of zero in the byte count field implies a transfer count of 64 Kbytes, which is the maximum
number of bytes that may be transferred per descriptor. Bit 7 of the upper byte of the second DWORD
contains an EOT (End-Of-Transfer) bit. The EOT bit indicates when the last data buffer is reached.
The GD31244 controller provides additional address registers to support PCI DAC cycles. For
example, an Upper DMA Descriptor Table Pointer Register and an Upper DMA Address Register are
defined. These registers allow the GD31244 controller to initiate PCI DAC cycles.
Note: The descriptor table must be aligned on a DWORD boundary, and must not cross a 64 Kbyte
boundary.
Note: The address field (data buffer address) in the descriptor must be aligned on a WORD boundary.
Furthermore, the data block must not cross a 64 Kbyte boundary.
Note: All the descriptors within a particular descriptor table share the same upper address register. For
example, all the data buffers must be within the same 4 Gbyte page.
In PCI IDE mode, the primary channel DMA registers are as follows:
• “SU IDE Channel 0 DMA Command Register - SUICDCR0” on page 178
• “SU IDE Channel 0 DMA Status Register - SUICDSR0” on page 179
• “SU IDE Channel 0 DMA Descriptor Table Pointer Register - SUICDDTPR0” on page 180
The secondary channel DMA are as follows:
• “SU IDE Channel 1 DMA Command Register - SUICDCR1” on page 181
• “SU IDE Channel 1 DMA Status Register - SUICDSR1” on page 182
• “SU IDE Channel 1 DMA Descriptor Table Pointer Register - SUICDDTPR1” on page 183.
In DPA mode, the DMA register are as follows:
• “SU PCI DPA Upper DMA Descriptor Table Pointer Register - SUPDUDDTPR” on page 215
• “SU PCI DPA Upper DMA Data Buffer Pointer Register - SUPDUDDPR” on page 216
• “SU PCI DPA DMA Command Register - SUPDDCMDR” on page 217
• “SU PCI DPA DMA Status Register - SUPDDSR” on page 218
• “SU PCI DPA DMA Descriptor Table Pointer Register - SUPDDDTPR” on page 219
Developer’s Manual
April 2004
55