EW31244SL7QV Datasheet, PDF (104/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
Figure 33.
The Serial ATA Unit includes two 8 byte and one 16-byte extended capability configuration spaces
beginning at configuration offset E0H, E8H and F0H. The extended configuration spaces may be
accessed by a device on the PCI interface through a mechanism defined in the PCI Local Bus
Specification, Revision 2.2.
In the SU Status Register (Section 5.10.2.4) the appropriate bit is set indicating that the Extended
Capability Configuration space is supported. When this bit is read, the device may then read the
Capabilities Pointer register (Section 5.10.2.20) to determine the configuration offset of the
Extended Capabilities Configuration Header. The format of these headers are depicted in Figure 33
through Figure 35.
SATA Unit Interface Extended Configuration Header Format (PCI-X Capability)
PCI-X Command
Next Item Pointer PCI-X Capability ID
E0H
PCI-X Status
E4H
.
Figure 34.
The first byte at the Extended Configuration Offset E0H is the PCI-X Capability Identifier Register
(Section 5.10.2.42). This will identify this Extended Configuration Header space as the type
defined by the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a.
Following the Capability Identifier Register will be the single byte Next Item Pointer Register
(Section 5.10.2.43) which will indicate the configuration offset of an additional Extended
Capabilities Header, when supported. In the SATA Unit, the Next Item Pointer Register is set to
E8H indicating that there are additional Extended Capabilities Headers supported in the SATA Unit
configuration space.
SU in PCI IDE Mode Interface Extended Configuration Header
Format (Power Management)
Power Management Capabilities
Reserved
Next Item Pointer Capability Identifier
Power Management Control/Status
E8H
ECH
The first byte at the Extended Configuration Offset E8H is the SATA Unit Capability Identifier
Register (Section 5.10.2.46). This will identify this Extended Configuration Header space as the
type defined by the PCI Bus Power Management Interface Specification, Revision 1.1.
Following the Capability Identifier Register will be the single byte Next Item Pointer Register
(Section 5.10.2.47) which will indicate the configuration offset of an additional Extended
Capabilities Header, when supported. In the Serial ATA Unit, the Next Item Pointer Register is set
to F0H indicating that there are additional Extended Capabilities Headers supported in the Serial
ATA Unit configuration space.
It is the configuration software responsibility to properly enable and initialize the SATA Unit
Power Management Interface.
104
April 2004
Developer’s Manual