EW31244SL7QV Datasheet, PDF (139/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.2.31 SU DMA Control Status Register- SUDCSCR
Table 69.
The control/status signals below are common to all four DMA channels or affect the Master
Transaction Controller. Control/status signals that are individual to each port are contained in the
Bus Master register set. See the description for the DMA Configuration register. Cache line
alignment is enabled in the DMA write (from controller to memory) direction unless the Cache
Line Size register is programmed with a value of 00h or an illegal value, in which case it is
disabled. The burst length can only take values greater than the cache line size. If an illegal value is
programmed for the burst length, the controller will internally use 40h for burst length, unless the
cache line size is programmed for 80h, in which case the controller will use 80h. The burst length
register is read/write and always returns the write value; if an illegal value is written, the corrected
internal value will not be visible on read back. Cache line alignment is normally disabled in the
DMA read direction. It may be enabled by setting bit 1.
SU DMA Control Status Register - SUDCSCR 0
PCI
Attributes
31
28
24
20
16
12
8
4
0
rv rv rv rw rw rv rv rv rv rv rv rv rv rv rv rw rw rw rw rw rw rv rw rw rv rv rv rv rv rw rw rw
Bit
31:29
28
27
26:16
15:08
07:03
02
01
00
PCI Configuration Address Offset
A0H - A3H
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
WO = Write Only
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Default
000₂
1₂
1
0
80h
0₂
0₂
0₂
0₂
Description
Reserved
Reserved
When HIGH, enables resets to the PCI/PCI-X core master transaction queue when bit 19 of the PCI-X
Capability Status register is cleared. This is necessary to recover from split responses that never get
completed due to a corrupted tag. Bit 19 of the PCI-X Capability Status register may also be set by an
unexpected split completion due to a corrupted requester ID for a split transaction that is not initiated by
this master. Clearing the queue in this case will not hurt even though the queue will have been correct.
For test purposes only; set only when there is no PCI traffic.
Reserved
DMA Burst Length: Bus master transaction burst length: This register contains the DMA burst length
value in [15:8]. This value sets the nominal PCI transaction burst length, other conditions permitting. The
resolution is 1 DWORD so the maximum in each case is 512 bytes and the minimum is 32 bytes. The
descriptor table defines the length of each physical region using physical region descriptors. The
Controller transfers each physical region in individual burst transactions.
• Reserved.
Block command disable. Set HIGH to disable the DMA engine from utilizing command types MWI and
MRM in PCI mode only. This bit does not effect PCI-X mode.
DMA write cache align enable. When HIGH, the controller will align with the cacheline address before
doing “burst length” transactions, total length permitting. When LOW, the controller will start with “burst
length” transaction, regardless of start address, total length permitting.
DMA read cache align enable. When HIGH, the controller will align with the cacheline address before
doing “burst length” transactions, total length permitting. When LOW, the controller will start with “burst
length” transaction, regardless of start address, total length permitting.
Developer’s Manual
April 2004
139