EW31244SL7QV Datasheet, PDF (134/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.2.26 SPI Command Register - SPICMDR
Serial Peripheral Interface (SPI) Command Register definition is described in Table 64. The host
writes the command type to the command register after setting up the control and data registers as
necessary. A write to this register initiates the command.
Table 64. SPI Command Register - SPICMDR
PCI
Attributes
7
4
0
rw rw rw rw rw rw rw rw
PCI Configuration Address Offset
90
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Bit
Default
Description
Expansion Rom SPI interface command type. A write to this initiates the command. The status
register bit D0 must be polled to determine when the command is complete.
06h = WREN (write enable)
04h = WRDI (write disable)
01h = WRSR (write status)
7:0
00
02h = No action (SPI PROGRAM command)
52h = SECT_ERASE (sector erase)
62h = CHIP_ERASE (all sector erase)
05h = RDSR (read status)
03h = No action (SPI READ command)
others = no action
134
April 2004
Developer’s Manual