EW31244SL7QV Datasheet, PDF (213/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.10 SU PCI DPA Mode Control Block Registers
This section defines the Control Block Registers.
5.10.10.1 SU PCI DPA Alternate Status Register - SUPDASR
Table 128.
The SU PCI DPA Alternate Status Register is an 8-bit read-only register. This register contains the
same information as the SU PCI DPA Status Register. The difference is that when this register is
read, any pending interrupt is not cleared. Refer to the AT Attachment with Packet Interface-6
(ATA/ATAPI-6) Specification.
SU PCI DPA Alternate Status Register - SUPDASR
PCI
Attributes
7
43
0
ro ro ro ro ro ro ro ro
DPA Mode BAR0 Offset
Port 0 = 228H, Port 1 = 428H
Port 2 = 628H, Port 3 = 828H
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Bit
07:00
Default
Description
Refer to
Table 126.
Alternate Status Register - This register contains the same information as in the IDE Status Register. The
difference is that when this register is read, any pending interrupts are not cleared. Refer to Section 126,
“SU PCI DPA Status Register - SUPDSR” on page 211.
Developer’s Manual
April 2004
213