EW31244SL7QV Datasheet, PDF (133/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.2.25 SU Maximum Latency Register - SUMLAT
SU Maximum Latency Register bit definitions adhere to PCI Local Bus Specification,
Revision 2.2. This register specifies how often the device needs to access the PCI bus in increments
of eight PCI clocks.
Table 63.
This register and the Minimum Grant Register are information-only registers which the
configuration uses to determine how often a bus master typically requires access to the PCI bus and
the duration of a typical transfer when it does acquire the bus. This information is useful in
determining the values to be programmed into the bus master latency timers and in programming
the algorithm to be used by the PCI bus arbiter.
SU Maximum Latency Register - SUMLAT
PCI
Attributes
7
4
0
ro ro ro ro ro ro ro ro
Bit
07:00
PCI Configuration Address Offset
3FH
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Default
01H
Description
Maximum latency specifies how often the core needs to gain access to the PCI bus. The value is
specified in 0.25 µs increments and assumes a 33 MHz clock. A value of 0Fh means the core needs to
gain access to the PCI bus every 130 PCI clocks, expressed as 3.75 µs in this register.
Developer’s Manual
April 2004
133