EW31244SL7QV Datasheet, PDF (176/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.4 SU PCI IDE Mode Control Block Registers
This section defines the Device Control and Alternate Status Registers.
5.10.4.1
Table 104.
SU IDE Device Control Register - SUIDCR
The SU IDE Device Control Register is a write-only register. When the SU IDE Device Control
Register is read, instead the SU IDE Alternate Status Register is read. The SU IDE Device Control
Register is used to initiate a software reset to the device. It is also used to enable/disable interrupt.
Refer to the AT Attachment with Packet Interface-6 (ATA/ATAPI-6) Specification.
SU IDE Device Control Register - SUIDCR
PCI
Attributes
7
4
0
wo rv rv rv rv wo wo rv
PCI IDE Mode BAR1/BAR3 Offset
= 02H
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
WO = Write Only
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Bit
Default
Description
High Order Byte (HOB Bit) - When operating in 48-bit LBA addressing mode, the Sector Count, Cylinder
Low, and Cylinder High registers act a 2-byte deep FIFOs. For example, each of these registers are
16-bit registers with access to only one byte at a time.
07
0₂
The HOB bit provides a mechanism for software to be able to read either byte. Setting this bit to one
allows reading the upper byte, while setting the HOB bit to zero allows reading the lower byte
06
0₂
Reserved.
05
0₂
Reserved.
04
0₂
Reserved.
03
0₂
Reserved.
02
0₂
SRST - This bit is used by the processor to do a software reset.
01
0₂
nIEN - Interrupt Enable, this bit when cleared enables the assertion of interrupt signal to the processor.
When set, interrupt to the processor is masked.
00
0₂
Reserved. This bit shall always be cleared.
176
April 2004
Developer’s Manual