EW31244SL7QV Datasheet, PDF (97/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
Table 33.
31244 Controller Error Reporting Summary - PCI Interface (Sheet 3 of 3)
Error Condition^a
(Bus Mode^b)
(MSI)
Unexpected Split
Completion
(PCI-X)
(PCI-X)
Bits Set in
SU Status Register
(SUSR^c)
or
SU PCI-X Status Register
(SUPCIXSR^d)
PCI IDE Mode
SU IDE Channel 0 DMA
Status Register (SUICDSR0)
or
SU IDE Channel 1 DMA
Status Register (SUICDSR1)
DPA Mode
SU PCI DMA Status Register
(SUPDDSR)
PCI Bus Error Response
(i.e., signal Target-Abort, signal
Master-Abort etc.)
DMA Action
DMA Action
SERR# Asserted - bit 14 of SUSR
In the PCI-X mode, the transaction
will complete normally according to
the invalid lower address field or
invalid byte count.
None
None
Unexpected Split Completion bit
set only for an unmatched Tag -
bit 19
None
None
a. All parity errors refer to data parity errors except where otherwise noted.
b. Codes for bus mode in which this error response applies: PCI-X means PCI-X Mode Only, Conventional means Conventional PCI Mode Only,
and Both means that the error response applies both in the Conventional and PCI-X mode of operation. MSI stands for Message-Signaled
Interrupts and refers to an Outbound Write transaction that is actually an MSI write transaction.
c. Table assumes that Parity Error Response - bit 6 of the SUCMD register is set.
d. Table assumes that Data Parity Recovery Enable - bit 0 of the SUPCIXCMD is clear.
e. When the SCE bit (bit 30 of the Completer Attributes) and the SCM bit (bit 29 of the Completer Attributes) are set during the Attribute phase of a
Split Completion Transaction, the transaction is a Split Completion Message that is an Error Message. In this case, the Received Split Completion
Error Message - bit 29 of the SUPCIXSR is set.
Developer’s Manual
April 2004
97