EW31244SL7QV Datasheet, PDF (177/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.4.2
Table 105.
SU IDE Alternate Status Register - SUIASR
The SU IDE Alternate Status Register is an 8-bit read-only register. When the SU IDE Alternate
Status Register is written to, instead the SU IDE Device Control Register is written. This register
contains the same information as the SU IDE Status Register, Table 102, “SU IDE Status Register -
SUISR” on page 174. The difference is that when this register is read, any pending interrupt is not
cleared. Refer to the AT Attachment with Packet Interface-6 (ATA/ATAPI-6) Specification.
SU IDE Alternate Status Register - SUIASR
PCI
Attributes
7
4
0
ro ro ro ro ro ro ro ro
PCI IDE Mode BAR1/BAR3 Offset
= 02H
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Bit
Default
Description
07:00
Refer to
Section 102,
“SU IDE Alternate Status Register - This register contains the same information as in the SU IDE Status Register.
Status The difference is that when this register is read, any pending interrupts are not cleared. Refer to
Register - Section 102, “SU IDE Status Register - SUISR” on page 174.
SUISR” on
page 174.
Developer’s Manual
April 2004
177