EW31244SL7QV Datasheet, PDF (236/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.12.12 SU PCI DPA Device BIST Data High Register - SUPDDBDHR
Table 146.
The SU PCI DPA Device BIST Data High Register is the second 32-bit parameter of the SATA Bist
Activate Device-to-Host FIS. Refer to the Serial ATA Specification.
SU PCI DPA Device BIST Data High Register - SUPDDBDHR
PCI
Attributes
31
28
24
20
16
12
8
4
0
ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro
PCI IDE Mode Offset
= 05CH,
DPA Mode Offset
Port 0 = 35CH, Port 1 = 55CH
Port 2 = 75CH, Port 3 = 95CH
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
Bit
Default
Description
31:00 0000_0000H This register contains the data transmitted as BIST FIS DWORD 2.
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
236
April 2004
Developer’s Manual