EW31244SL7QV Datasheet, PDF (94/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.6.6
SERR# Assertion and Detection
The GD31244 controller is capable of reporting error conditions through the use of the SERR#
output.
The following conditions may result in the assertion of SERR# by the GD31244 controller:
• An address parity error (or an attribute parity error when operating in the PCI-X mode) is
detected by the GD31244 controller PCI interface (see Section 5.6.1, “Address and Attribute
Parity Errors on the PCI Interface” on page 83 for details).
• A Master Data Parity Error is recorded in the SUSR while operating in the PCI-X mode (see
Section 5.6.2, “Data Parity Errors on the PCI Interface” on page 84 for details).
• An outbound MSI write transaction is either signaled a Master-Abort or a Target-Abort by the
target.
The following actions with the given constraints are performed by the GD31244 controller when
SERR# is asserted by the GD31244.
• Set the SERR# Asserted bit in the SUSR.
Note: GD31244 does not detect SERR# on the bus, and does not take any action for SERR#
asserted by other PCI/X devices.
94
April 2004
Developer’s Manual