EW31244SL7QV Datasheet, PDF (223/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
Table 136. SU PCI DPA SATA SError Register - SUPDSSER (Sheet 2 of 3)
PCI
Attributes
31
28
24
20
16
12
8
4
0
rv rv rv rv rv rv rc rv rv rc rc rc rv rc rv rc rv rv rv rv rc rc rc rc rv rv rv rv rv rv rc rv
PCI IDE Mode BAR5 Offset
= 004H,
DPA Mode BAR0 Offset
Port 0 = 304H, Port 1 = 504H
Port 2 = 704H, Port 3 = 904H
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Bit
19
18
17
16
15-12
11
10
09
08
07:02
Default
Description
0₂
0₂
0₂
0₂
0000₂
0₂
DIAG_B - not implemented.
DIAG_W - Comm Wake:
When set to one, this bit indicates that a Comm Wake was detected by the PHY. This bit is cleared by
writing a 1 to it. The default value after reset is 0₂. After Comm Wake is detected, the value will change
to 1₂.
DIAG_I - Reserved, not implemented.
DIAG_N - PHYRDY Change State:
When set to one this bit indicates that the PHYRDY signal changed state. State change means going
from READY to NOT-READY or NOT-READY to READY. This bit shall remain cleared when the PHY
was not detected as ready during the initialization process. When the PHY goes ready after initialization,
this bit shall transition to 1. This bit is cleared by writing a 1 to it. This bit is reported as an interrupt on bit
0, 8, 16, and 24 of the SATA Interrupt Pending register for SATA ports 0, 1, 2, and 3 respectively. Refer
to Table 116, “SU PCI DPA Interrupt Pending Register - SUPDIPR” on page 194.
The default value after reset is 0₂, for example the PHY will not be ready. When the PHY becomes
ready (state change from not-ready to ready) as part of the initialization sequence, the value will change
to 1₂.
Reserved.
ERR_E - Internal Error:
This bit indicates that a FIFO error occurred due to a FIFO overrun or underrun condition. This bit is
cleared by writing a 1 to it. This bit is reported as an interrupt on bit 2, 10, 18, and 26 of the SATA
Interrupt Pending register for SATA ports 0, 1, 2, and 3 respectively. Refer to Table 116, “SU PCI DPA
Interrupt Pending Register - SUPDIPR” on page 194.
ERR_P - Protocol Error:
This bit when set indicates that a corrupted FIS was received. This bit may indicate that the FIS
0₂
received was an invalid FIS type or that the received FIS was not properly structured. For example,
incorrect length. This bit is cleared by writing a 1 to it. This bit is reported as an interrupt on bit 4, 12, 20,
and 28 of the SATA Interrupt Pending register for SATA ports 0, 1, 2, and 3 respectively. Refer to
Table 116, “SU PCI DPA Interrupt Pending Register - SUPDIPR” on page 194.
Varies with
the signal
level of the
PHY receive
path
ERR_C - Non-Recovered Communication:
This is an asynchronous signal which reflects the signal level of the PHY receive path. When high, this
bit indicates that there is no signal detected on the PHY receive path (RX). This may occur from a faulty
interconnect, removal of a device, or the signal level is simply below the reference point.
ERR_T - Non-Recovered Transient Data Integrity Error:
This bit indicates that either a CRC error, disparity error, or the receipt of an R_ERR primitive occurred
0₂
in response to a Data FIS. This bit is cleared by writing a 1 to it. This bit is reported as an interrupt on bit
5, 13, 21, and 29 of the SATA Interrupt Pending register for SATA ports 0, 1, 2, and 3 respectively. Refer
to Table 116, “SU PCI DPA Interrupt Pending Register - SUPDIPR” on page 194.
000000₂ Reserved
Developer’s Manual
April 2004
223